A New Design Method of GDDR6 WCLK Using Reinforcement Learning for over 20Gbps

Abstract

The data rate of GDDR6 is required over 20Gbps. Signal integrity of DQ is essential to keep the data rate of GDDR6 at 2XGbps. GDDR6 divides WCK and creates internal data clock (iWCK) for use in DQ SerDes. For signal integrity of DQ, skew between iWCKs should be minimized. To this end, iWCK skew must be accurately measured in Automatic test equipment (ATE) and managed from the design stage. In this study, an accurate method for measuring iWCK skew is proposed. A simulation environment is also proposed to match the ATE measurement results. Based on the proposed simulation environment, an iWCK design optimization method using reinforcement learning is also proposed. In order to verify the proposed design optimization method, a skew reduction target was set to 30% and reinforcement learning was conducted. As a result, a schematic that satisfies the target value was obtained. The proposed design optimization method is simple and powerful because only the design target needs to be set.