Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM)

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dc.contributor.authorKim, SeongGukko
dc.contributor.authorKim, Jounghoko
dc.contributor.authorShin, TaeInko
dc.contributor.authorPark, Hyunwookko
dc.contributor.authorLho, Daehwanko
dc.contributor.authorSon, Keeyoungko
dc.contributor.authorKim, Keunwooko
dc.contributor.authorPark, Joonsangko
dc.contributor.authorChoi, Seongukko
dc.contributor.authorKim, Haeyeonko
dc.date.accessioned2023-02-02T01:00:37Z-
dc.date.available2023-02-02T01:00:37Z-
dc.date.created2023-01-25-
dc.date.issued2021-12-13-
dc.identifier.citationIEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2021-
dc.identifier.issn2151-1225-
dc.identifier.urihttp://hdl.handle.net/10203/304938-
dc.description.abstractIn this paper, we proposed the design of a spiral through-silicon via (TSV) array channel for high bandwidth memory (HBM) with 8 Gbps data transmission. In 12-stacked HBM, we design the spiral TSV array including the physical structure and pin assignment to reduce channel loss and via-to-via crosstalk. To verify the proposed channel, the channel model is extracted by a high-frequency structure simulator (HFSS). The electrical performance is simulated and analyzed in the frequency and time domains. As a result, the proposed design successfully improves eye height and width at 8 Gbps compared to the conventional spiral TSV array.-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleSignal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM)-
dc.typeConference-
dc.identifier.scopusid2-s2.0-85124170738-
dc.type.rimsCONF-
dc.citation.publicationnameIEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2021-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationUrbana-
dc.identifier.doi10.1109/EDAPS53774.2021.9657033-
dc.contributor.localauthorKim, Joungho-
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EE-Conference Papers(학술회의논문)
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