Steep-Slope Transistor with an Imprinted Antiferroelectric Film

Abstract

The effect of negative capacitance (NC), which can internally boost the voltage applied to a transistor, has been considered to overcome the fundamental Boltzmann limit of a transistor. To stabilize the NC effect, the dielectric (DE) must be integrated into a heterostructure with a ferroelectric (FE) film. However, in a multidomain hafnia, the charge boosting effect is reduced owing to a lowering of the depolarization field originating from the stray field at each domain, and simultaneously, the operating voltage increases owing to the voltage division at the DE. Here, we demonstrate core approaches to the gate stack of energy-efficient device technology using a transient NC. Electrical measurements of the transistor with imprinted antiferroelectric and high CDE/CFE structures exhibit low subthreshold slopes below 20 mV/dec, a low voltage operation of 0.5 V, a fast operation of 20 ns, hysteresis-free Id-Vg, and high endurance characteristics of 1012 cycles. We expect that this will lead to the rapid implementation of the NC effect in high-speed switching device applications with significantly improved energy efficiency.