DC Field | Value | Language |
---|---|---|
dc.contributor.author | Myoung Hoon Yoon | ko |
dc.contributor.author | Yang, Kyoung-Hoon | ko |
dc.date.accessioned | 2022-12-15T02:00:26Z | - |
dc.date.available | 2022-12-15T02:00:26Z | - |
dc.identifier.uri | http://hdl.handle.net/10203/303040 | - |
dc.description.abstract | When InP DHBTs are located in parallel to a crystallographical direction of 003c#011003e#, there are several advantages in the aspect of device property such as reliability. But, in case of a direction parallel to a general 003c#011003e#, there exists the limitation in reducing base-collector parasitic capacitance only by collector over-etching technique due to poor lateral-etching characteristic of the InP collector. To overcome such a problem mentioned above and improve device performance, the present invention provides a method of reducing parasitic capacitance using underneath crystallographically selective wet etching, thereby providing a self-alignable, structurally stable device. | - |
dc.title | Method of reducing device parasitic capacitance using underneath crystallographically selective wet etching | - |
dc.title.alternative | 하부 결정학적으로 선택적 습식 에칭을 사용한 소자 기생 커패시턴스 감소 방법 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | Yang, Kyoung-Hoon | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 10271246 | - |
dc.identifier.patentRegistrationNumber | 06780702 | - |
dc.date.application | 2002-10-15 | - |
dc.date.registration | 2004-08-24 | - |
dc.publisher.country | US | - |
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