A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter

Abstract

With the increasing demand for low-power, high-speed DRAMs, LPDDR5 featuring a speed of 6.4Gb/s has recently been announced [1]. One of the most critical issues of high-performance DRAM is the supply-noise induced jitter (SIJ) generated by the clock distribution network (CDN) and the transmit and receive paths. Conventional CDN SIJ coping methods use supply voltage regulators and decoupling capacitors. Unfortunately, a supply regulator is not suitable for low-voltage mobile DRAM due to the required drop-out voltage headroom, while the decoupling capacitor cannot sufficiently filter low-frequency noise without requiring excessive area. In this paper, we propose an SIJ cancelation technique based on an adaptive filter (AF) using a least mean square (LMS) algorithm; it cancels jitter along the CDN and the transmit and receive paths, which include serializers and pre-drivers. The proposed technique includes a 2nd-order AF to maximize jitter cancellation in the clock path, which has a non-linear supply-to-jitter characteristic [2]. Implemented in 28nm CMOS, the proposed SIJ cancellation scheme reduces the RMS jitter of the RDQSc clock from 27.33 to 4.20ps and improves the data eye opening from 22.34 to 99.12ps when operating at 6.4Gb/s with a 60mV_p-p 1 MHz supply noise.