A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator

Abstract

To generate low-jitter, high-frequency signals with ring oscillators (ROs), injection-locked clock multipliers (ILCMs) are the most suitable architecture due to advantages such wide bandwidth and fewer noise sources. However, they have two inherent issues. The first is that their jitter performance is sensitive to PVT variations. To address this problem, recent RO-ILCMs have been equipped with a multi-purpose, real-time digital calibrator that can remove both the frequency error of the RO and the phase error of the calibrator [1]-[2]. The second is that their operational stability and jitter performance degrade rapidly as the multiplication factor, N, increases. This issue, which has yet to be well addressed, is rooted in the fundamental limitation of the typical injection-locking method, i.e., injecting narrow pulses into the RO (top left of Fig. 13.2.1). When the free-running frequency of the RO deviates from the target frequency, Nf- REF, where f- REF is the frequency of the reference clock (mathcalS- REF), the core current of the RO (I-osc) and the injecting current (I-INJ) should be out of phase to satisfy the oscillation condition by creating the necessary phase shift. Thus, the effective magnitude of I-INJ at N f- REF, i.e., I-INJ, eff , relative to l-osc determines the maximum phase angle, phi-MAX, and, thus, the maximum lock range, omega-L, MAX [3]. However, for a large N, I-INJ, eff becomes extremely small, sharply reducing phi-MAX and omega-L, MAX. Although the RO-ILCMs in [4]-[5] achieved a total N of over 40 by using a reference doubler or quadrupler, their two-stage operation offers limited improvement of the jitter FoM. MDLL-based implementations are better suited for larger N, but the time required for edge switching limits the maximum output frequency, f-OUT, and the value of N.