Vertical-Pillar Ferroelectric Field-Effect-Transistor Memory

Abstract

In recent years, following trends in developing semiconductors, extensive research has been conducted to develop a hafnia-based ferroelectric field effect transistor (FeFET) memory. However, its fundamental endurance limitation, which stems from early degradation of the gate insulator, has been a major obstacle to the development of FeFETs, with no clear solution despite attempting various approaches to high-speed and high-reliability FeFETs. Herein, a novel metal-ferroelectric-metal-insulator-semiconductor FeFET with vertical-pillar channel and metal-ferroelectric-metal capacitor (VP-FeFET) that can adjust the capacitance ratio between the ferroelectric film and gate insulator by modulating the channel height is proposed. The optimized VP-FeFET exhibits a significantly reduced electric field (<= 1.5 MV cm(-1)) through the gate insulator, resulting in a substantially enhanced FeFET endurance. Furthermore, the proposed FeFET achieved a large memory window of approximate to 5 V and a high program/erase speed of approximate to 100 ns. These merits are achieved without increasing the footprint of the FeFET device. This approach to high-performance FeFET can be applied extensively to next-generation nonvolatile memory devices.