DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Sangho | ko |
dc.contributor.author | Kim, Giuk | ko |
dc.contributor.author | Kim, Taeho | ko |
dc.contributor.author | Eom, Taehyong | ko |
dc.contributor.author | Jeon, Sanghun | ko |
dc.date.accessioned | 2022-10-18T02:01:55Z | - |
dc.date.available | 2022-10-18T02:01:55Z | - |
dc.date.created | 2022-01-04 | - |
dc.date.created | 2022-01-04 | - |
dc.date.created | 2022-01-04 | - |
dc.date.issued | 2022-10 | - |
dc.identifier.citation | PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS, v.16, no.10 | - |
dc.identifier.issn | 1862-6254 | - |
dc.identifier.uri | http://hdl.handle.net/10203/299016 | - |
dc.description.abstract | In recent years, following trends in developing semiconductors, extensive research has been conducted to develop a hafnia-based ferroelectric field effect transistor (FeFET) memory. However, its fundamental endurance limitation, which stems from early degradation of the gate insulator, has been a major obstacle to the development of FeFETs, with no clear solution despite attempting various approaches to high-speed and high-reliability FeFETs. Herein, a novel metal-ferroelectric-metal-insulator-semiconductor FeFET with vertical-pillar channel and metal-ferroelectric-metal capacitor (VP-FeFET) that can adjust the capacitance ratio between the ferroelectric film and gate insulator by modulating the channel height is proposed. The optimized VP-FeFET exhibits a significantly reduced electric field (<= 1.5 MV cm(-1)) through the gate insulator, resulting in a substantially enhanced FeFET endurance. Furthermore, the proposed FeFET achieved a large memory window of approximate to 5 V and a high program/erase speed of approximate to 100 ns. These merits are achieved without increasing the footprint of the FeFET device. This approach to high-performance FeFET can be applied extensively to next-generation nonvolatile memory devices. | - |
dc.language | English | - |
dc.publisher | WILEY-V C H VERLAG GMBH | - |
dc.title | Vertical-Pillar Ferroelectric Field-Effect-Transistor Memory | - |
dc.type | Article | - |
dc.identifier.wosid | 000734292700001 | - |
dc.identifier.scopusid | 2-s2.0-85121702822 | - |
dc.type.rims | ART | - |
dc.citation.volume | 16 | - |
dc.citation.issue | 10 | - |
dc.citation.publicationname | PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS | - |
dc.identifier.doi | 10.1002/pssr.202100532 | - |
dc.contributor.localauthor | Jeon, Sanghun | - |
dc.contributor.nonIdAuthor | Lee, Sangho | - |
dc.contributor.nonIdAuthor | Eom, Taehyong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | backend-of-the-line | - |
dc.subject.keywordAuthor | ferroelectric field effect transistor | - |
dc.subject.keywordAuthor | ferroelectrics | - |
dc.subject.keywordAuthor | HfO2 | - |
dc.subject.keywordAuthor | vertical-pillar transistors | - |
dc.subject.keywordPlus | FET | - |
dc.subject.keywordPlus | HF0.8ZR0.2O2 | - |
dc.subject.keywordPlus | RELIABILITY | - |
dc.subject.keywordPlus | CHARGE | - |
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