SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation

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dc.contributor.authorChoi, Edward Jongyoonko
dc.contributor.authorChoi, Injunko
dc.contributor.authorJeon, Chanheeko
dc.contributor.authorYun, Gichanko
dc.contributor.authorYi, Donghyeonko
dc.contributor.authorHa, Sohmyungko
dc.contributor.authorChang, Ik-Joonko
dc.contributor.authorJe, Minkyuko
dc.date.accessioned2022-10-17T09:00:42Z-
dc.date.available2022-10-17T09:00:42Z-
dc.date.created2022-10-17-
dc.date.created2022-10-17-
dc.date.issued2022-
dc.identifier.citationIEEE SOLID-STATE CIRCUITS LETTERS, v.5, pp.234 - 237-
dc.identifier.issn2573-9603-
dc.identifier.urihttp://hdl.handle.net/10203/298997-
dc.description.abstractIn this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient "one-step" method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleSRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation-
dc.typeArticle-
dc.identifier.scopusid2-s2.0-85139381387-
dc.type.rimsART-
dc.citation.volume5-
dc.citation.beginningpage234-
dc.citation.endingpage237-
dc.citation.publicationnameIEEE SOLID-STATE CIRCUITS LETTERS-
dc.identifier.doi10.1109/LSSC.2022.3206416-
dc.contributor.localauthorJe, Minkyu-
dc.contributor.nonIdAuthorJeon, Chanhee-
dc.contributor.nonIdAuthorHa, Sohmyung-
dc.contributor.nonIdAuthorChang, Ik-Joon-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCapacitors-
dc.subject.keywordAuthorRandom access memory-
dc.subject.keywordAuthorLayout-
dc.subject.keywordAuthorComputer architecture-
dc.subject.keywordAuthorTransistors-
dc.subject.keywordAuthorStandards-
dc.subject.keywordAuthorCommon Information Model (computing)-
dc.subject.keywordAuthorCharge domain computation-
dc.subject.keywordAuthorcomputing-in-Memory (CIM)-
dc.subject.keywordAuthorconvolutional neural network (CNN)-
dc.subject.keywordAuthormixed-signal computation-
dc.subject.keywordAuthorstatic random-access memory (SRAM)-
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