DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Edward Jongyoon | ko |
dc.contributor.author | Choi, Injun | ko |
dc.contributor.author | Jeon, Chanhee | ko |
dc.contributor.author | Yun, Gichan | ko |
dc.contributor.author | Yi, Donghyeon | ko |
dc.contributor.author | Ha, Sohmyung | ko |
dc.contributor.author | Chang, Ik-Joon | ko |
dc.contributor.author | Je, Minkyu | ko |
dc.date.accessioned | 2022-10-17T09:00:42Z | - |
dc.date.available | 2022-10-17T09:00:42Z | - |
dc.date.created | 2022-10-17 | - |
dc.date.created | 2022-10-17 | - |
dc.date.issued | 2022 | - |
dc.identifier.citation | IEEE SOLID-STATE CIRCUITS LETTERS, v.5, pp.234 - 237 | - |
dc.identifier.issn | 2573-9603 | - |
dc.identifier.uri | http://hdl.handle.net/10203/298997 | - |
dc.description.abstract | In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient "one-step" method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation | - |
dc.type | Article | - |
dc.identifier.scopusid | 2-s2.0-85139381387 | - |
dc.type.rims | ART | - |
dc.citation.volume | 5 | - |
dc.citation.beginningpage | 234 | - |
dc.citation.endingpage | 237 | - |
dc.citation.publicationname | IEEE SOLID-STATE CIRCUITS LETTERS | - |
dc.identifier.doi | 10.1109/LSSC.2022.3206416 | - |
dc.contributor.localauthor | Je, Minkyu | - |
dc.contributor.nonIdAuthor | Jeon, Chanhee | - |
dc.contributor.nonIdAuthor | Ha, Sohmyung | - |
dc.contributor.nonIdAuthor | Chang, Ik-Joon | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Capacitors | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Layout | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Transistors | - |
dc.subject.keywordAuthor | Standards | - |
dc.subject.keywordAuthor | Common Information Model (computing) | - |
dc.subject.keywordAuthor | Charge domain computation | - |
dc.subject.keywordAuthor | computing-in-Memory (CIM) | - |
dc.subject.keywordAuthor | convolutional neural network (CNN) | - |
dc.subject.keywordAuthor | mixed-signal computation | - |
dc.subject.keywordAuthor | static random-access memory (SRAM) | - |
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