DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Jang, Young Jae | - |
dc.contributor.advisor | 장영재 | - |
dc.contributor.author | Cho, Hyemin | - |
dc.date.accessioned | 2022-04-27T19:32:34Z | - |
dc.date.available | 2022-04-27T19:32:34Z | - |
dc.date.issued | 2021 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=948325&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/296226 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 지식서비스공학대학원, 2021.2,[iv, 36 p. :] | - |
dc.description.abstract | We address Bayesian approach for the layout design problem of semiconductor AMHS fab in dynamic routing environment. This thesis focuses on the installation problem of the bypass track, which is installed for the purpose of avoiding congested areas in the overhead hoist transport (OHT) system. The purpose of the study is to search for a bypass installation combination which minimizes the average delivery time through minimal sampling. The performance of the methodology based on combinatorial Bayesian optimization is compared with the heuristic and Genetic algorithm. When compared with the Genetic algorithm, Bayesian algorithm acquires the same result obtained with less sampling. Through the results of the study, the possibility of using Bayesian methodology for the layout design problem is suggested. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Semiconductor▼aAMHS▼aTrack layout design▼aOverhead hoist transport system▼aCombinatorial optimization▼aBayesian optimization | - |
dc.subject | 반도체▼a자동 반송 시스템▼a트랙 레이아웃 설계▼a동적 경로 탐색▼a조합 최적화▼a베이지안 최적화 | - |
dc.title | Semiconductor fab AMHS track layout design for dynamic routing environment using combinatorial Bayesian optimization | - |
dc.title.alternative | 조합 베이지안 최적화를 활용한 동적 라우팅 환경에서의 반도체 AMHS 팹 트랙 레이아웃 디자인 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :지식서비스공학대학원, | - |
dc.contributor.alternativeauthor | 조혜민 | - |
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