Routability optimization for low aspect ratio design

Abstract

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. We observe that non-uniform setting of utilization target greatly helps in these designs, specifically low utilization in the center and gradually higher utilization toward the ends. We introduce a convolutional neural network (CNN) model to predict the setting of utilization target values. Clock wires and clock buffers added after clock tree synthesis (CTS) cause overflows that were not present in the placement stage. In this paper, a method of predicting the overflow region caused by CTS in the pre-CTS stage and reducing the overflow through flip-flop clustering and relocation was also proposed. Experiments indicate that routing congestion overflows are reduced by 29\% on average of test designs with 40% reduction in wirelength. Routable chip areas are averagely reduced by 18% than commercial tool and clock buffers are also reduced by 32%.