(A) low-power low-jitter 10GHz frequency synthesizer for 60GHz heterodyne system

Abstract

High-order modulation in the 60GHz band is required to achieve a data rate of several tens of Gbps, and the jitter characteristic of the frequency synthesizer is an important performance to achive high order modulation. To this end, this study deals with a low-power, low-jitter 10GHz frequency synthesizer for a heterodyne 60GHz wireless communication system. The 10GHz frequency synthesizer was fabricated using a 65nm CMOS process. In this study, in order to achieve low power, a divider with multiple division ratio combined with logical operation functions was designed. In addition, in order to achieve low spur performance, a charge pump having a symmetrical structure was designed. The maximum RMS jitter of the 10GHz phase-locked loop is 371fs, and the spur is -55dBc. The power consumption of the 10GHz phase locked loop is 5.77mW, and the multi-modulus divider for low power consumes 0.12mW power. Finally, low power performance due to the proposed divider was achieved, and also improved spur performance through the proposed charge pump.