Offset-mismatch-free pseudo-loop-unrolled SAR ADC

Abstract

This work presents a loop-unrolled successive approximation register (LU SAR) ADC without additional calibration. Conventional LU SAR ADCs have several comparators per each bit to remove the delay, therefore the mismatches between them degrade the performance of ADCs. Proposed ADC adopts the modified double-tail comparator which shares the preamplifier and separates the latches. Since the input-referred offset between the latches is reduced by the gain of the pre-amplifier, it does not require calibration. It enables a speed-enhanced architecture compared to the conventional SAR ADC with a compact area. The prototype 6-bit 700-MS/s SAR ADC was implemented in CMOS 28-nm process and has 0.0012 mm2 small area. With Nyquist input, the measured signal-to-noise- and-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) are 34.34 and 49.97 dB, respectively consuming 1 mW. The ADC achieves 33.8 fJ/conversion step Walden figure-of-merit (FOM) at 700-MS/s.