Wafer flow time control of track systems for semiconductor manufacturing

Abstract

We examine wafer flow times in a track system for coating and developing processes in photolithography process for semiconductor fabrication. A track system consists of two cluster tools, one for coating photoresist on wafer surfaces to be exposed to a circuit pattern at a scanner and another for developing the exposed circuit pattern. A coater performs pre-baking, coating, baking, and cooling in series. Since the baking and cooling processes take long, they are performed by several parallel processing modules to balance the workload between the process steps. Due to space restriction, they are stacked up. The wafer handling robot should access the vertically stacked modules which increase the wafer flow times and their variance. The average and variance of the wafer flow times in the coating process before scanning tend to increase wafer quality degradation and variability. The developer also has similar scheduling issues. To reduce and control wafer flow times and their variance in such a cluster tool with vertically stacked processing modules, we first develop a timed even graph model for the tool behavior and identify the work cycle and its sub-cycles. By examining the timed event graph model and the sub-cycles, we then prove that the schedule can repeat an identical timing pattern for each cycle and develop a formula for computing wafer flow times. Then, we propose the robot’s access order to parallel modules at each process step that can reduce wafer flow times and their variance. We also propose a way of intentionally postponing some robot tasks to reduce the wafer flow time variance. We propose a feedback control method to further control the tools robustly to reduce starvation or blocking at a small buffer between the scanner and the coater or developer. We show effectiveness of the proposed methods by simulation experiments.