Curing of 1-Transistor-DRAM by Joule Heat From Punch-Through Current

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dc.contributor.authorKim, Hyun-Jungko
dc.contributor.authorLee, Geon-Beomko
dc.contributor.authorHan, Joon-Kyuko
dc.contributor.authorHan, Seong-Jooko
dc.contributor.authorKim, Da-Jinko
dc.contributor.authorYu, Ji-Manko
dc.contributor.authorKim, Myung-Suko
dc.contributor.authorChoi, Yang-Kyuko
dc.date.accessioned2022-04-14T06:45:51Z-
dc.date.available2022-04-14T06:45:51Z-
dc.date.created2022-02-28-
dc.date.created2022-02-28-
dc.date.created2022-02-28-
dc.date.issued2022-03-
dc.identifier.citationIEEE ELECTRON DEVICE LETTERS, v.43, no.3, pp.370 - 373-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10203/292777-
dc.description.abstractThe 1-transistor-DRAM (1T-DRAM) with a floating body is iteratively operated and deteriorated as the number of programming cycles is increased. This aging results an increase in the interface trap density ( Nit) . Internal electro-thermal annealing (ETA) using Joule heat generated by punch-through current flowing from the source via the channel to the drain, reduces the Nit and eventually cures the operating damage of the 1T-DRAM. To quantitatively analyze the Nit before and after curing, a synchronized optical charge pumping (SOCP) method that is applicable even to a floating body (FB) device, was used. By adopting self-curing during 1T-DRAM operations, endurance was notably increased by reducing Nit . It is expected that aged 1T-DRAMs can be recovered when such ETA is enabled at the moment of system rebooting.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleCuring of 1-Transistor-DRAM by Joule Heat From Punch-Through Current-
dc.typeArticle-
dc.identifier.wosid000761656500012-
dc.identifier.scopusid2-s2.0-85124077747-
dc.type.rimsART-
dc.citation.volume43-
dc.citation.issue3-
dc.citation.beginningpage370-
dc.citation.endingpage373-
dc.citation.publicationnameIEEE ELECTRON DEVICE LETTERS-
dc.identifier.doi10.1109/LED.2022.3147259-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorKim, Hyun-Jung-
dc.contributor.nonIdAuthorHan, Seong-Joo-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorStressLogic gatesCuringHeating systemsTemperature measurementGallium arsenideField effect transistorsCuringelectro-thermal annealing (ETA)floating body (FB)gate-all-around (GAA)hot-carrier injection (HCI)interface trap densityJoule heat1-transistor-DRAM (1T-DRAM)single transistor latch (STL)punch-throughsynchronized optical charge pumping (SOCP)-
dc.subject.keywordPlusLEAKAGE CURRENTMODEL-
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