DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Taikyu | ko |
dc.contributor.author | Choi, Cheol Hee | ko |
dc.contributor.author | Byeon, Pilgyu | ko |
dc.contributor.author | Lee, Miso | ko |
dc.contributor.author | Song, Aeran | ko |
dc.contributor.author | Chung, Kwun-Bum | ko |
dc.contributor.author | Han, Seungwu | ko |
dc.contributor.author | Chung, Sung-Yoon | ko |
dc.contributor.author | Park, Kwon-Shik | ko |
dc.contributor.author | Jeong, Jae Kyeong | ko |
dc.date.accessioned | 2022-01-24T06:40:39Z | - |
dc.date.available | 2022-01-24T06:40:39Z | - |
dc.date.created | 2022-01-24 | - |
dc.date.created | 2022-01-24 | - |
dc.date.created | 2022-01-24 | - |
dc.date.issued | 2022-01 | - |
dc.identifier.citation | NPJ 2D MATERIALS AND APPLICATIONS, v.6, no.1 | - |
dc.identifier.issn | 2397-7132 | - |
dc.identifier.uri | http://hdl.handle.net/10203/292003 | - |
dc.description.abstract | Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm(2) V-1 s(-1) and an I-ON/OFF ratio of 5.8 x 10(5) with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of similar to 75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration. | - |
dc.language | English | - |
dc.publisher | NATURE PORTFOLIO | - |
dc.title | Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity | - |
dc.type | Article | - |
dc.identifier.wosid | 000742364000002 | - |
dc.identifier.scopusid | 2-s2.0-85123048280 | - |
dc.type.rims | ART | - |
dc.citation.volume | 6 | - |
dc.citation.issue | 1 | - |
dc.citation.publicationname | NPJ 2D MATERIALS AND APPLICATIONS | - |
dc.identifier.doi | 10.1038/s41699-021-00280-7 | - |
dc.contributor.localauthor | Chung, Sung-Yoon | - |
dc.contributor.nonIdAuthor | Kim, Taikyu | - |
dc.contributor.nonIdAuthor | Choi, Cheol Hee | - |
dc.contributor.nonIdAuthor | Lee, Miso | - |
dc.contributor.nonIdAuthor | Song, Aeran | - |
dc.contributor.nonIdAuthor | Chung, Kwun-Bum | - |
dc.contributor.nonIdAuthor | Han, Seungwu | - |
dc.contributor.nonIdAuthor | Park, Kwon-Shik | - |
dc.contributor.nonIdAuthor | Jeong, Jae Kyeong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | TOTAL-ENERGY CALCULATIONS | - |
dc.subject.keywordPlus | LATTICE-DYNAMICS | - |
dc.subject.keywordPlus | LARGE-AREA | - |
dc.subject.keywordPlus | PHASE | - |
dc.subject.keywordPlus | NANOWIRES | - |
dc.subject.keywordPlus | GRAPHENE | - |
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