Word-line and Charge-pump modeling of NAND Flash using Standard CMOS Logic Process

Abstract

The industry has increased the word line (WL) layer to improve the density of 3D NAND flash. As the WL layer increases, the energy consumed to generate the boosted WL voltage has also increased. In 3D NAND flash, understanding the block configuration and operation of a word line driver (WL driver) with high energy consumption should be preceded to implement a 3D NAND flash with low energy consumption. This study presents a conventional WL driver for triple-level cell 3D NAND flash to understand the operation and classify energy consumption. The conventional WL driver for a 56-WL layer is fabricated in 180nm UHV process, and it consumes 141.15nJ from a 2.2V during 1 unit of program pulse and verify period.