An offset charge compensating biphasic neuro-stimulation for faradaic DC-current reduction
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Cho, Donghyeok | ko |
| dc.contributor.author | Koo, Nahmil | ko |
| dc.contributor.author | Jang, Taekwang | ko |
| dc.contributor.author | Cho, SeongHwan | ko |
| dc.date.accessioned | 2021-11-05T06:42:24Z | - |
| dc.date.available | 2021-11-05T06:42:24Z | - |
| dc.date.created | 2021-10-26 | - |
| dc.date.created | 2021-10-26 | - |
| dc.date.created | 2021-10-26 | - |
| dc.date.issued | 2021-05 | - |
| dc.identifier.citation | IEEE International Symposium on Circuits and Systems (IEEE ISCAS) | - |
| dc.identifier.issn | 0271-4310 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/288892 | - |
| dc.description.abstract | In this paper, we analyze faradaic DC current (FC) generated by inherent offset charge (IOC) and charge mismatch. Under frequent shorting, the analysis shows that mismatch-induced DC current is small compared to IOC-induced DC current. To reduce the FC, we propose a biphasic pulse scheme which compensates the IOC. Simulation results show the proposed pulse scheme reduces the FC by about 58 times compared to a conventional biphasic pulse. | - |
| dc.language | English | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | An offset charge compensating biphasic neuro-stimulation for faradaic DC-current reduction | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000706507900244 | - |
| dc.identifier.scopusid | 2-s2.0-85108994548 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | IEEE International Symposium on Circuits and Systems (IEEE ISCAS) | - |
| dc.identifier.conferencecountry | KO | - |
| dc.identifier.conferencelocation | Daegu | - |
| dc.identifier.doi | 10.1109/ISCAS51556.2021.9401722 | - |
| dc.contributor.localauthor | Cho, SeongHwan | - |
| dc.contributor.nonIdAuthor | Jang, Taekwang | - |
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