DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Juhyoung | ko |
dc.contributor.author | Kim, Sangyeob | ko |
dc.contributor.author | Kim, Sangjin | ko |
dc.contributor.author | Jo, Wooyoung | ko |
dc.contributor.author | Han, Donghyeon | ko |
dc.contributor.author | Lee, Jinsu | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2021-11-05T06:41:58Z | - |
dc.date.available | 2021-11-05T06:41:58Z | - |
dc.date.created | 2021-10-26 | - |
dc.date.issued | 2021-06 | - |
dc.identifier.citation | 35th Symposium on VLSI Circuits, VLSI Circuits 2021 | - |
dc.identifier.issn | 2158-5601 | - |
dc.identifier.uri | http://hdl.handle.net/10203/288887 | - |
dc.description.abstract | This paper presents OmniDRL, a 4.18 TFLOPS and 29.3 TFLOPS/W DRL processor. A group-sparse training core and exponent mean delta encoding are proposed to enable weight and feature map compression for every iteration of DRL training. A sparse weight transposer enables on-chip transpose of compressed weight for reducing external memory access. The processor fabricated in 28 nm CMOS technology and occupies 3.6×3.6 mm2 die area. It achieved 7.16 TFLOPS/W energy efficiency for training robot agent (Mujoco Halfcheetah, TD3), which is 2.4× higher than the previous state-of-the-art. © 2021 JSAP. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer | - |
dc.type | Conference | - |
dc.identifier.scopusid | 2-s2.0-85111890717 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 35th Symposium on VLSI Circuits, VLSI Circuits 2021 | - |
dc.identifier.conferencecountry | JA | - |
dc.identifier.doi | 10.23919/VLSICircuits52068.2021.9492504 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Jo, Wooyoung | - |
dc.contributor.nonIdAuthor | Lee, Jinsu | - |
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