DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Sujin | ko |
dc.contributor.author | Chae, Hangil | ko |
dc.contributor.author | Cho, SeongHwan | ko |
dc.date.accessioned | 2021-11-04T06:45:10Z | - |
dc.date.available | 2021-11-04T06:45:10Z | - |
dc.date.created | 2021-10-26 | - |
dc.date.created | 2021-10-26 | - |
dc.date.issued | 2021-06 | - |
dc.identifier.citation | 35th Symposium on VLSI Circuits, VLSI Circuits 2021 | - |
dc.identifier.uri | http://hdl.handle.net/10203/288794 | - |
dc.description.abstract | This paper presents an ultra-high-resolution energy-efficient 4th-order continuous-time (CT) bandpass (BP) Σ capacitance-to-digital converter (CDC) where thermal noise folding is avoided by CT operation and power is saved by using a BP Σ architecture. The proposed CDC achieves a resolution of 3.68 aFrms at room temperature while achieving a Schreier figure-of-merit (FoMS) of 183dB which is more than 2x improvement over the state-of-the-art CDCs. © 2021 JSAP. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A 3.68aFrmsResolution 183dB FoMs 4th-order Continuous-Time Bandpass Σ Capacitance-to-Digital Converter in 0.18μm CMOS | - |
dc.type | Conference | - |
dc.identifier.scopusid | 2-s2.0-85111815397 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 35th Symposium on VLSI Circuits, VLSI Circuits 2021 | - |
dc.identifier.conferencecountry | JA | - |
dc.identifier.conferencelocation | Virtual | - |
dc.identifier.doi | 10.23919/VLSICircuits52068.2021.9492366 | - |
dc.contributor.localauthor | Cho, SeongHwan | - |
dc.contributor.nonIdAuthor | Chae, Hangil | - |
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