A 3.68aFrmsResolution 183dB FoMs 4th-order Continuous-Time Bandpass Σ Capacitance-to-Digital Converter in 0.18μm CMOS

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dc.contributor.authorPark, Sujinko
dc.contributor.authorChae, Hangilko
dc.contributor.authorCho, SeongHwanko
dc.date.accessioned2021-11-04T06:45:10Z-
dc.date.available2021-11-04T06:45:10Z-
dc.date.created2021-10-26-
dc.date.created2021-10-26-
dc.date.issued2021-06-
dc.identifier.citation35th Symposium on VLSI Circuits, VLSI Circuits 2021-
dc.identifier.urihttp://hdl.handle.net/10203/288794-
dc.description.abstractThis paper presents an ultra-high-resolution energy-efficient 4th-order continuous-time (CT) bandpass (BP) Σ capacitance-to-digital converter (CDC) where thermal noise folding is avoided by CT operation and power is saved by using a BP Σ architecture. The proposed CDC achieves a resolution of 3.68 aFrms at room temperature while achieving a Schreier figure-of-merit (FoMS) of 183dB which is more than 2x improvement over the state-of-the-art CDCs. © 2021 JSAP.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleA 3.68aFrmsResolution 183dB FoMs 4th-order Continuous-Time Bandpass Σ Capacitance-to-Digital Converter in 0.18μm CMOS-
dc.typeConference-
dc.identifier.scopusid2-s2.0-85111815397-
dc.type.rimsCONF-
dc.citation.publicationname35th Symposium on VLSI Circuits, VLSI Circuits 2021-
dc.identifier.conferencecountryJA-
dc.identifier.conferencelocationVirtual-
dc.identifier.doi10.23919/VLSICircuits52068.2021.9492366-
dc.contributor.localauthorCho, SeongHwan-
dc.contributor.nonIdAuthorChae, Hangil-
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EE-Conference Papers(학술회의논문)
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