Off-state leakage in MOSFET considering source/drain extension regions

Abstract

Transistors have reached the extremely small dimensions of sub-10 nm in this era. Gate length has always been primarily considered for the scaling-down of CMOS technologies, but the total contacted poly pitch is the key to achieving a high packing density chip. In this work, the source/drain extension region is taken into consideration to investigate off-state leakage, especially for band-to-band tunneling and Schottky tunneling leakage. Various device parameters were modified within the dimensions of state-of-the-art transistors in the latest semiconductor roadmap. This study was carried out with the aid of the TCAD simulator calibrated using nonequilibrium Green's function simulation.