DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Seok-Hee | ko |
dc.contributor.author | Moon, Jung-Min | ko |
dc.contributor.author | Kim, Tae-Kyun | ko |
dc.date.accessioned | 2021-07-30T00:31:31Z | - |
dc.date.available | 2021-07-30T00:31:31Z | - |
dc.identifier.uri | http://hdl.handle.net/10203/286936 | - |
dc.description.abstract | A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity. | - |
dc.title | Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same | - |
dc.title.alternative | 무접합 수직 게이트 트랜지스터를 갖는 반도체 소자 및 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | Lee, Seok-Hee | - |
dc.contributor.nonIdAuthor | Moon, Jung-Min | - |
dc.contributor.nonIdAuthor | Kim, Tae-Kyun | - |
dc.contributor.assignee | KAIST, SK hynix Inc. | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 16398118 | - |
dc.identifier.patentRegistrationNumber | 10892262 | - |
dc.date.application | 2019-04-29 | - |
dc.date.registration | 2021-01-12 | - |
dc.publisher.country | US | - |
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