DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoo, Seyeon | ko |
dc.contributor.author | Park, Suneui | ko |
dc.contributor.author | Choi, Seojin | ko |
dc.contributor.author | Cho, Yoonseo | ko |
dc.contributor.author | Yoon, Heein | ko |
dc.contributor.author | Hwang, Chanwoong | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2021-07-29T05:30:16Z | - |
dc.date.available | 2021-07-29T05:30:16Z | - |
dc.date.created | 2021-07-29 | - |
dc.date.issued | 2021-02-13 | - |
dc.identifier.citation | 2021 IEEE International Solid- State Circuits Conference (ISSCC) | - |
dc.identifier.issn | 0193-6530 | - |
dc.identifier.uri | http://hdl.handle.net/10203/286901 | - |
dc.description.abstract | As the utilization of the mm-wave spectrum becomes active, designers' interests are shifting to even higher frequencies in the W-band. Given their potential use as carrier frequencies for the next-generation mobiles (i.e., beyond 5G), these W-band signals must have ultra-low phase noise (PN). Currently, the most popular solution to generate such frequencies is with a cascaded architecture: a first-stage PLL generates a low-PN signal at a relatively low frequency at which the VCO LC tank has a high Q factor, and following frequency multipliers (FMs) increase the frequency to the W-band [1]. Although various FMs have been proposed, all of them are limited in their ability to achieve a high multiplication factor, M. Push-push or harmonic-selection circuits have high conversion losses. Injection-locked FMs (ILFMs) require multiple stages due to their narrow lock ranges, which increase power consumption and complexity. Thus, single-stage direct PLLs [2] -[4] would be preferred if they could have a sufficiently wide loop bandwidth to suppress the poor PN of a W-band VCO. Subsampling PLLs (SSPLLs) are suitable for extending the bandwidth since they have low in-band PN due to the high phase-error \left(\phi_{\text {ERR}}\right) detection gain of a subsampling phase detector (PD). Nevertheless, when SSPLLs operate in the W-band, the degradation of PN is unavoidable because the \phi_{\text {ERR}} detection gain decreases as the frequency of the VCO, f_{\text {vco}}, increases. As described at the left of Fig. 23.4.1, when the switch of the \mathrm{PD}, S W_{\mathrm{PD}}, is closed, the output of the \mathrm{PD}, S_{\mathrm{PD}}, should track the signal of the VCO, S_{\text {vco}}, closely. However, when f_{\text {vco}} increases to the W-band, the amplitude of S_{\mathrm{PD}} is reduced significantly by a parasitic pole that is present due to the turned-on resistance of S W_{\mathrm{PD}}, R_{\mathrm{ON}}, and the sampling capacitor, C_{\mathrm{S}} When S W_{\mathrm{PD}} is turned off, \phi_{\mathrm{ERR}} is detected in S_{\mathrm{PD}}, but its magnitude is already suppressed significantly relative to that in S_{\mathrm{vCO}}. This effect also can be interpreted in the frequency domain where S_{\text {vco}} is suppressed by a low-pass filter before the information of \phi_{\text {ERR}} is extracted at the baseband frequencies. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS | - |
dc.type | Conference | - |
dc.identifier.wosid | 000662193600130 | - |
dc.identifier.scopusid | 2-s2.0-85102360217 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2021 IEEE International Solid- State Circuits Conference (ISSCC) | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Francisco, CA | - |
dc.identifier.doi | 10.1109/isscc42613.2021.9365956 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Yoo, Seyeon | - |
dc.contributor.nonIdAuthor | Park, Suneui | - |
dc.contributor.nonIdAuthor | Choi, Seojin | - |
dc.contributor.nonIdAuthor | Cho, Yoonseo | - |
dc.contributor.nonIdAuthor | Yoon, Heein | - |
dc.contributor.nonIdAuthor | Hwang, Chanwoong | - |
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