Channel estimation and sequence detection for 1-bit ADC and time-oversampling receiver

Abstract

In the high data rate communication system, the high power consumption of analog-to-digital converters (ADCs) with high resolution in amplitude domain should be addressed. Therefore, 1-bit ADC system has been considered to be a promising architecture. Several studies have dealt with maximizing the achievable data rate in 1-bit ADC system by combining time-oversampling at the receiver. There are previous works providing the sequence design for pulse amplitude modulation (PAM) using the Markov source in additive Gaussian noise (AWGN) channel. However, the modifying distribution of source is another challenge. This paper proposes a systematic mapper-demapper architecture, which is suitable for independent uniformly distributed source. Moreover, we provide the minimum oversampling factor for PAM in AWGN channel. We enlarged the the mapper-demapper system for PAM into QAM. Unfortunately, the transceiver scheme developed in AWGN channel cannot be used in fading channel. Various papers treat the channel estimation issues based on the Bussgang theorem. However, the saturation in performances of the Bussgang theorem based estimators is pointed out. To avoid such problem, the design of pilot sequence and maximum likelihood estimator for channel phase, the critical channel parameter in 1-bit ADC system, is proposed in this paper. The performance of proposed estimator approaches to the ideal performance in high SNR regime in terms of frame error rate when the compensation of phase is assumed based on the estimated channel phase.