Processing-in-memory of high bandwidth memory (PIM-HBM) architecture with efficient channels for energy efficiency and high performance in artificial Intelligence (AI) servers

Abstract

In this paper, we firstly propose processing-in-memory in high bandwidth memory (PIM-HBM) architecture with efficient channels for energy efficiency and high performance in artificial intelligence servers. The main concept of the proposed PIM-HBM architecture is to embed processing units into a logic layer of high bandwidth memory (HBM) to decrease the energy consumption of interconnection and increase the data bandwidth of dynamic random-access memory (DRAM). Based on the area and configuration of the HBM, the proposed architecture is designed considering the physical feasibility. In addition, on-chip, interposer, and through silicon via (TSV) channels are designed and analyzed for the proposed architecture. To verify the proposed PIM-HBM architecture, the energy consumption, delay, and bandwidth of the channel are obtained through circuit simulation, and the energy efficiency and performance of the proposed architecture are evaluated by an architectural simulation embedding the result of the circuit simulation.