Metal-oxide-semiconductor capacitance modeling of through-silicon vias for high density 3-D ICs

Abstract

Through-silicon via (TSV) technology has emerged as a key component of three-dimensional (3-D) integrated circuits (ICs). As the integration density in a package increases, the nonlinear metal-oxide-semiconductor (MOS) capacitance in TSVs has a greater effect on the electrical performance of the devices. Charge type imperfections due to the deposition of a dielectric layer are important factors which can change the characteristics of the MOS capacitance. In this dissertation, we proposed a rigorous MOS capacitance modeling of TSVs for 3-D ICs. MOS capacitance and depletion region can be modelled by the nonlinear Poisson’s equation including the charge type imperfections. In the procedures to solve this equation, the proposed method considers not only the tempera-ture effect of intrinsic carrier concentration and silicon bandgap energy, but also the shift effect of the flat band voltage due to the charge type imperfections. The MOS capacitance model is proposed using this solution and two applications using this model are presented. First, a method for determining a keep-out zone (KOZ) for 3-D ICs is presented. An increase in the TSV density causes the charge carrier mobility in neighboring semiconductor devices to be influenced more by the electric field (E-field) around the TSV. The KOZ is required to ensure the proper operation of 3-D ICs using TSVs given these negative effects. Second, a method for detecting the interface-trap charge density (D$_{it}$) and lateral nonuniformity (LNU) of charge type imperfections in TSVs is presented. In particular, as the LNU is known to be an important cause of the stress-induced leakage current in the dielectric material, in order to ensure the reliability of the system, the methods for determining whether the LNU exists in TSV and eliminating this LNU must be devised.