Clock generation techniques to mitigate supply-noise effect

Abstract

With CMOS processes scaling, transistor sizes decrease and the integration technology is advanced. Since there are many transistors switching at a wide spectrum of frequencies, the supply voltage suffers from dynamic variations. In particular, as the supply voltage continues to decrease, the problem caused by supply noise becomes more serious. This thesis analyzes the effects of the supply noise of the clock generator and introduces several techniques to minimize the performance degradation caused by these effects. By presenting a solution according to applications, we optimize a clock generation circuit design that can be used in each application. First, for a clock generator that is insensitive to supply noise, we introduce an oscillator that can detect and correct frequency changes due to noise without an external reference clock. This uses a wide bandwidth feedback loop around the oscillator to suppress supply noise without loss of headroom, unlike prior techniques that use a low-dropout regulator. Second, an adaptive clock technique that changes the clock frequency in response to supply noise is presented. This prevents malfunction in applications such as microprocessors and optimizes power and frequency performance. To this end, we introduce a technique to minimize the response time for supply noise by placing the clock modulator after the clock buffer. In addition, it utilizes a background calibration loop that automatically tracks the frequency and supply sensitivity of the clock modulator to maximize frequency performance during supply noise.