(A) study on performance enhancement techniques for sub-ranging SAR ADC범위 분할 연속 근사 아날로그–디지털 변환기의 성능 향상 기법에 대한 연구

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dc.contributor.advisorRyu, Seung-Tak-
dc.contributor.advisor류승탁-
dc.contributor.authorRoh, Yi-Ju-
dc.date.accessioned2021-05-12T19:45:16Z-
dc.date.available2021-05-12T19:45:16Z-
dc.date.issued2020-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=924520&flag=dissertationen_US
dc.identifier.urihttp://hdl.handle.net/10203/284432-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2020.8,[iv, 40 p. :]-
dc.description.abstractSuccessive approximation register (SAR) analog-to-digital converters (ADCs) have been developed with tremendous performance improvement during the last decade mainly due to their low-power, simple and digital-friendly architecture. However, the conversion speed that is inversely proportional to the resolution remains as one of the fundamental design bottlenecks, due to the increased number of decision cycles with a required digital-to-analog converter (DAC) settling accuracy in every decision cycle. To enhance the conversion speed of a SAR ADC, several architectural modifications could be tried. Time-interleaved (TI) architecture could be a good selection as a solution for increased number of decision cycles. In addition, as the conversion is more burdensome in the MSB part in terms of both settling speed and power consumption, subranging architecture could alleviate this issue with a fast and compact coarse ADC. So, in this paper, a SAR-assisted 4-way time interleaved SAR ADC that uses a double rate coarse ADC operation is presented. The coarse ADC operates with a higher rate operation to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using series switching, loop-unrolled comparators, redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The single channel ADC core occupies a $0.0128-mm^2$ area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step. The 4-way interleaved ADC has TI timing initialization issues due to processing failure, the time-interleaving operation did not work properly, so the only temporary measurement was possible. The measured SNDR and SFDR were 48 dB and 57 dB, and the ADC occupies a $0.06-mm^2$.-
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectSAR ADC▼atime-interleaved ADC▼asub-ranging architecture▼aSAR-assisted SAR ADC▼asubranging SAR ADC▼anonbinary SAR ADC▼anonbinary metastable error correction method-
dc.subject연속 근사 아날로그 디지털 변환기▼a시분할 아날로그 디지털 변환기▼a비이진 아날로그 디지털 변환기▼a범위 분할 아날로그 디지털 변환기▼a비이진 준 안정성 문제 해결기법-
dc.title(A) study on performance enhancement techniques for sub-ranging SAR ADC-
dc.title.alternative범위 분할 연속 근사 아날로그–디지털 변환기의 성능 향상 기법에 대한 연구-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN325007-
dc.description.department한국과학기술원 :전기및전자공학부,-
dc.contributor.alternativeauthor노이주-
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