(A) framed-pulsewidth-modulation scheme for next generation high-speed communication links

Abstract

A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the SNR degradation without linearity requirement is presented. The FPWM scheme encodes data at the location and the width of pulses in a frame spanning multiple UIs while maintaining a minimum pulsewidth equal to 1UI. The test-chip achieves a coding gain of 33%, which allows the total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at transmitter and continuous-time linear equalizer (CTLE) at receiver compensates for channel insertion loss up to 12 dB at the baud frequency. The transceiver IC, fabricated in 40 nm CMOS, occupies $2.2 \times 0.48 mm^2$ and consumes 90.6 mW from a 0.9 V supply.