Ultra-low-power convultional neural network-based face recognition system

Abstract

A low-power convolutional neural network (CNN)-based face recognition (FR) system is proposed for user authentication in smart devices. The system consists of two chips: an always-on functional CMOS image sensor (CIS) for imaging and face detection (FD) and a low-power CNN processor (CNNP) for face verification (FV). A functional CIS integrated with an FD accelerator enables event-driven chip-to-chip communication for only face images only when there is a face. To achieve low power consumption in FD while maintaining the memory size required for the FD processing not to exceed the on-chip memory size, two-stage FD using an analog FD unit and a digital FD unit is presented. For the event-driven FV, the CNNP adopts dynamic voltage and frequency scaling (DVFS) to minimize the power consumption when the number of faces in input images changes dynamically. In addition, tensor decomposition is used to reduce the workload of a CNN, and the CNNP architecture based on transpose-read SRAM (T-SRAM) allows low power consumption by reducing the local memory access. Implemented in 65nm CMOS technology, the $3.30\times3.36mm^2$ functional CIS and the $4\times4mm^2$ CNNP consume 0.62mW to evaluate one face at 1fps and achieve 97% accuracy in LFW dataset.