Layout design and optimization for self-aligned double patterning process

Abstract

With a scaling down of technology, multiple patterning has been introduced as an alternative for current ArF lithography in the minimum feature patterning

in particular, SADP is more suitable for fine resolution and pattern alignment among other multiple patterning methods. We propose layout design and optimization method in SADP process. First, in order to reduce wire delay in timing critical paths, wire width optimization is performed. The problem is formulated using a graph, a maximum weight independent set corresponds to an ideal solution. Second, to enhance chip yield, we propose RV insertion but it requires another cut (RV cut) to be introduced, which may cause coloring conflicts or design rule violations with adjacent line-end cuts. Thus, we address integrated RV insertion and cut optimization problem. Given a via layout, the problem is formulated for RV cut and line-end cut together as ILP, and a fast heuristic method is proposed for large circuits. RV insertion is maximized by solving the MIS problem. Lastly, we propose integrated routing and dummy fill, in which main design (routing, to be specific) and dummy fill insertion are performed together. A grid-based dummy arrays are first assumed

as a main design is introduced, array patterns are cut where needed to identify main routing as well as dummy fills.