(A) study on the radiation hardening design against both single event effect and total ionization dose effect

Abstract

In this dissertation, design methods of radiation-tolerant electronic components against a single event effect and a total ionizing dose effect in radiation environment are proposed. The proposed memory structure and unit device structures are designed to solve the problem of the single event effect and total ionizing dose effect. This dissertation consists of three chapters except introduction and conclusion. Radiation-tolerant flip-flop structure, silicon-on-insulator (SOI) based radiation-hardened unit MOSFET and bulk-silicon based radiation-hardened unit MOSFET are described in each chapter.

A flip-flop structure is proposed for radiation hardening, in which the inverter in the conventional flip-flop structure is replaced with a C-element including a delay component. The proposed flip-flop structure was simulated to evaluate its radiation tolerance against a single-event single-node upset and single-event multiple-node upset while applying single-event pulses. The single-event pulses were modeled by a particle transport simulator and a device TCAD simulator at multiple nodes. The simulation results demonstrated that the proposed flip-flop caused no upsets, whereas the conventional flip-flop exhibited numerous upsets. To verify the applicability of the proposed flip-flop to radiation-hardened circuits, a 50-stage shift register was fabricated using Magna & Hynix $0.18-\mum$ technology and compared with shift registers based on the conventional master-slave flip-flop and on the 4CE flip-flop. The shift register with the proposed flip-flop showed no upsets at a high dose of $5.22 \times 10^{12} protons/cm^2$ with an energy level of 70.0 MeV.

A dummy-gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) structure was modified to allow the use of a SOI substrate and evaluated for robustness against the total ionizing dose effect. The modified DGA n-MOSFET on the SOI substrate suppressed all possible radiation-induced leakage current paths by isolating both the drain and source from the sidewall oxide using a p+ layer, and from the buried oxide using dummy gates and halo doping. Simulated $V_g-I_d$ curves indicated that the modified DGA n-MOSFET on the SOI substrate effectively reduces the leakage current caused by accumulated radiation exposure. Furthermore, experimental gamma radiation exposure data showed that the modified device exhibited good performance, even after exposure up to 300 krad (Si). All devices used in the experiments were fabricated using the 180 nm commercial fabrication process by the CSOI7RF of Global Foundries (GF), formerly IBM Microelectronics.

A unit n-MOSFET hardened against both the total ionizing dose effect and single event effect is proposed on a bulk silicon substrate. Compared to conventional MOSFETs, the proposed MOSFET also possesses a dummy gate, p+ layer, dummy drain, n-well, and deep n-well. It can suppress all possible radiation-induced leakage current paths by isolating both the drain and source from the sidewall oxide using the p+ layer and dummy gates. It can also reduce the radiation-induced pulse current using the dummy drains, n-well, and deep n-well. Experimental data from the $V_g–I_d$ curves and radiation-induced pulse currents indicate that the proposed n-MOSFET effectively reduces the leakage current caused by accumulated radiation exposure and the pulse current caused by incident energetic particles. Furthermore, radiation experimental results for SRAM, designed with the proposed MOSFETs, indicate a good performance even after exposure to up to 1 Mrad (Si) and $3.8 \times 10^{13} protons/cm^2$ with an energy of 100 MeV. All devices used in the experiments were fabricated using the $0.35-\mum$ commercial fabrication process by Magna & Hynix.