DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Dong-Ryeol | ko |
dc.contributor.author | Moon, Kyoung-Jun | ko |
dc.contributor.author | Lim, Won-Mook | ko |
dc.contributor.author | Kim, Ye-Dam | ko |
dc.contributor.author | An, Eun-Ji | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2021-04-26T04:50:13Z | - |
dc.date.available | 2021-04-26T04:50:13Z | - |
dc.date.created | 2021-04-26 | - |
dc.date.created | 2021-04-26 | - |
dc.date.issued | 2021-04 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.4, pp.1216 - 1226 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/282544 | - |
dc.description.abstract | An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-SAR ADC and a reference-embedding 8x interpolating flash (I-Flash) ADC to enhance the conversion speed. Operating the CDAs in a dual-edge manner makes it possible to achieve an 8-bit resolution with only four CDAs and one capacitive digital-to-analog converter (C-DAC), which improves the power and area efficiency as well as the input bandwidth. A prototype ADC implemented in a 28-nm CMOS process occupies a 0.002 mm(2) active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration is 0.59 and 0.82 LSB, respectively. With a 0.499-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 45.5 and 59.4 dB, respectively. The measured effective resolution bandwidth (ERBW) is above 3 GHz. The power consumption at 1-GS/s conversion is 2.55 mW with a supply voltage of 1.1 V, leading to a figure of merit (FoM) of 16.6 fJ/conversion-step. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000662229500019 | - |
dc.identifier.scopusid | 2-s2.0-85099093217 | - |
dc.type.rims | ART | - |
dc.citation.volume | 56 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 1216 | - |
dc.citation.endingpage | 1226 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2020.3044624 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Lim, Won-Mook | - |
dc.contributor.nonIdAuthor | An, Eun-Ji | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | complementary dynamic amplifier (CDA) | - |
dc.subject.keywordAuthor | hybrid ADC | - |
dc.subject.keywordAuthor | interpolating flash (I-Flash) ADC | - |
dc.subject.keywordAuthor | loop unrolled (LU) successive approximation register (SAR) ADC | - |
dc.subject.keywordAuthor | offset calibration | - |
dc.subject.keywordAuthor | SAR-Flash | - |
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