DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Jinsu | ko |
dc.contributor.author | Kang, Sanghoon | ko |
dc.contributor.author | Lee, Jinmook | ko |
dc.contributor.author | Shin, Dongjoo | ko |
dc.contributor.author | Han, Donghyeon | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2021-03-26T01:51:40Z | - |
dc.date.available | 2021-03-26T01:51:40Z | - |
dc.date.created | 2020-10-19 | - |
dc.date.issued | 2020-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.10, pp.3458 - 3470 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/281863 | - |
dc.description.abstract | Deep neural network (DNN) has been widely studied due to its high performance and usability for various applications such as image classification, detection, segmentation, translation, and action recognition. Thanks to the universal applications and high performance of DNN algorithm, DNN is adopted for various AI platforms, including edge/mobile devices as well as cloud servers. However, high-performance DNN requires a large amount of computation and memory access, making it challenging to implement DNN operation on edge/mobile. There have been several ways to solve these problems, including algorithms as well as hardware for DNN. Algorithms that help accelerate DNN in hardware enable much more efficient operation of high-performance AI. This article aims to provide an overview of the recent hardware and algorithm co-design schemes enabling efficient processing of DNNs. Specifically, it will provide algorithm optimization methods for DNN structure, neurons, synapses, and data types. This paper also introduces optimization methods for hardware architectures, PE array, data-path control, and microarchitecture of PE. And we will also show examples of DNN algorithm and hardware co-designed ASICs. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices | - |
dc.type | Article | - |
dc.identifier.wosid | 000574745600020 | - |
dc.identifier.scopusid | 2-s2.0-85092733571 | - |
dc.type.rims | ART | - |
dc.citation.volume | 67 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 3458 | - |
dc.citation.endingpage | 3470 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2020.3021397 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Hardware | - |
dc.subject.keywordAuthor | Optimization | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Neurons | - |
dc.subject.keywordAuthor | Artificial intelligence | - |
dc.subject.keywordAuthor | Performance evaluation | - |
dc.subject.keywordAuthor | Synapses | - |
dc.subject.keywordAuthor | Application specific integrated circuit (ASIC) | - |
dc.subject.keywordAuthor | co-design | - |
dc.subject.keywordAuthor | deep learning (DL) | - |
dc.subject.keywordAuthor | deep neural network (DNN) | - |
dc.subject.keywordAuthor | energy efficient hardware | - |
dc.subject.keywordAuthor | hardware friendly algorithm | - |
dc.subject.keywordAuthor | machine learning (ML) | - |
dc.subject.keywordPlus | DEEP NEURAL-NETWORKS | - |
dc.subject.keywordPlus | ACCELERATOR | - |
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