Reed solomon decoder and semiconductor device including the same

Abstract

A Reed Solomon decoder may include a syndrome calculation (SC) circuit, a key equation solver (KES) circuit, and a Chien search and error evaluation (CSEE) circuit. The SC circuit calculates a syndrome from a codeword. The KES circuit includes a plurality of sub-KES circuit and calculates an error location polynomial and an error evaluation polynomial from the syndrome. The CSEE circuit calculates an error location and an error value from the error location polynomial and the error evaluation polynomial. Each of the plurality of sub-KES circuits, the SC circuit and the CSEE circuit respectively constitute pipeline stages. The Read Solomon decoder may also include a FIFO queue that queues the codeword among a plurality of codewords sequentially received, and an error correction circuit that produces error corrected data using an output from the FIFO queue, the error location, and the error value.