Understanding size effects in the advanced through-silicon via interconnect schemes for 3D ICs

Abstract

Synchrotron X-ray microdiffraction has been successfully used to unravel how stresses evolve both in Cu through silicon via (TSV) as well as in silicon surrounding it. These findings have led to much improvements in solving the integration issues (pop-up/bulging of TSV during annealing, silicon delamination/fracture, etc.) as well as enhancing reliability and performance (reducing the 'keep-away zone.') in the microelectronics devices in the last 5 years. However, today's microelectronics world has moved further into smaller and smaller technology nodes including the TSV diameters and pitches. This report will describe some of our most recent findings on the systematic studies of size effects using TSV samples fabricated with all the same fabrication methodology provided by SK Hynix, Inc. with diameters 2μm, 5μm and 8μm. Our investigation showed the smaller the TSV diameters, the stress is not necessary the smaller and thus suggested that such smaller technology could lead to further integration issues and potentially reliability and performance concerns.