DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Hongseok | ko |
dc.contributor.author | Kim, Jinuk | ko |
dc.contributor.author | Jang, Doojin | ko |
dc.contributor.author | Cho, Donghee | ko |
dc.contributor.author | Jung, Yoontae | ko |
dc.contributor.author | Cho, Hyungjoo | ko |
dc.contributor.author | Lee, Unbong | ko |
dc.contributor.author | Kim, Chul | ko |
dc.contributor.author | Ha, Sohmyung | ko |
dc.contributor.author | Je, Minkyu | ko |
dc.date.accessioned | 2021-02-04T07:30:12Z | - |
dc.date.available | 2021-02-04T07:30:12Z | - |
dc.date.created | 2020-12-08 | - |
dc.date.created | 2020-12-08 | - |
dc.date.created | 2020-12-08 | - |
dc.date.issued | 2020-12 | - |
dc.identifier.citation | IEEE SOLID-STATE CIRCUITS LETTERS, v.3, pp.530 - 533 | - |
dc.identifier.issn | 2573-9603 | - |
dc.identifier.uri | http://hdl.handle.net/10203/280579 | - |
dc.description.abstract | This letter presents a high-gain energy-efficient three-stage amplifier, which employs buffering-based pole relocation and dual-path structure. The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth (GBW) of the local feedback loop (LFL). Compared to the topologies using active-zero insertion, the 3rd pole is formed with a much smaller capacitance (parasitic capacitance), enabling it to be placed at a significantly higher frequency while consuming lower power. Moreover, the parasitic pole at the main path is bypassed by using an auxiliary path. Thus, the 3rd pole can be pushed to a higher frequency more easily than the topologies using an active zero. As a result, the GBW of the LFL in the proposed work is less limited. The proposed design improves the state-of-the-art FOML by 36%, LC-FOMS by 26%, and LC-FOML by 218%, while preserving robustness of the performance. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | An Energy-Efficient Three-Stage Amplifier Achieving a High Unity-Gain Bandwidth for Large Capacitive Loads without Using a Compensation Zero | - |
dc.type | Article | - |
dc.identifier.scopusid | 2-s2.0-85096372573 | - |
dc.type.rims | ART | - |
dc.citation.volume | 3 | - |
dc.citation.beginningpage | 530 | - |
dc.citation.endingpage | 533 | - |
dc.citation.publicationname | IEEE SOLID-STATE CIRCUITS LETTERS | - |
dc.identifier.doi | 10.1109/lssc.2020.3036496 | - |
dc.contributor.localauthor | Kim, Chul | - |
dc.contributor.localauthor | Je, Minkyu | - |
dc.contributor.nonIdAuthor | Kim, Jinuk | - |
dc.contributor.nonIdAuthor | Ha, Sohmyung | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Capacitive load | - |
dc.subject.keywordAuthor | energy efficiency | - |
dc.subject.keywordAuthor | frequency compensation | - |
dc.subject.keywordAuthor | three-stage amplifier | - |
dc.subject.keywordAuthor | unity-gain frequency | - |
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