Parallel operation of Self-Limited Analog Programming for Fast Array-Level Weight Programming and Update

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dc.contributor.authorSong, Hanchanko
dc.contributor.authorAn, Janghoko
dc.contributor.authorSon, Seoilko
dc.contributor.authorKim, Young Seokko
dc.contributor.authorPark, Juseongko
dc.contributor.authorJeon, Jae Bumko
dc.contributor.authorKim, Geunyoungko
dc.contributor.authorKim, Kyung Minko
dc.date.accessioned2021-01-05T10:30:03Z-
dc.date.available2021-01-05T10:30:03Z-
dc.date.created2020-06-24-
dc.date.created2020-06-24-
dc.date.created2020-06-24-
dc.date.created2020-06-24-
dc.date.issued2020-07-
dc.identifier.citationAdvanced Intelligent Systems, v.2, no.7, pp.2000014-
dc.identifier.issn2640-4567-
dc.identifier.urihttp://hdl.handle.net/10203/279530-
dc.description.abstractMemristive neural networks perform vector matrix multiplication efficiently, which is used for the accelerator of neuromorphic computing. To train the memristor cells in a memristive neural network, the analog conductance state of the memristor should be programmed in parallel; otherwise, the resulting long training time can limit the size of the neural network. Herein, a novel parallel programming method using the self‐limited analog switching behavior of the memristor is proposed. A Pt/Ti:NbOx/NbOx/TiN charge trap memristor device for the programming demonstration is utilized, and a convolutional neural network is emulated to train the MNIST dataset, based on the device characteristics. In the simulation, the proposed programming method is able to reduce programming time to as low as 1/130, compared with the sequential programming method. The simulation suggests that the programming time required by the proposed method is not affected by array size, which makes it very promising in a high‐density neural network.-
dc.languageEnglish-
dc.publisherWilley Online Library-
dc.titleParallel operation of Self-Limited Analog Programming for Fast Array-Level Weight Programming and Update-
dc.typeArticle-
dc.identifier.wosid000669780200007-
dc.type.rimsART-
dc.citation.volume2-
dc.citation.issue7-
dc.citation.beginningpage2000014-
dc.citation.publicationnameAdvanced Intelligent Systems-
dc.identifier.doi10.1002/aisy.202000014-
dc.contributor.localauthorKim, Kyung Min-
dc.contributor.nonIdAuthorSong, Hanchan-
dc.contributor.nonIdAuthorAn, Jangho-
dc.contributor.nonIdAuthorSon, Seoil-
dc.contributor.nonIdAuthorKim, Young Seok-
dc.contributor.nonIdAuthorPark, Juseong-
dc.contributor.nonIdAuthorJeon, Jae Bum-
dc.contributor.nonIdAuthorKim, Geunyoung-
dc.description.isOpenAccessY-
dc.type.journalArticleArticle-
dc.subject.keywordAuthoranalog programming-
dc.subject.keywordAuthorstateful logic-
dc.subject.keywordAuthorneuromorphic devices-
dc.subject.keywordAuthorself-limited switching-
dc.subject.keywordAuthormemristors-
dc.subject.keywordPlusNEURAL-NETWORK-
dc.subject.keywordPlusLOW-POWER-
dc.subject.keywordPlusMEMRISTOR-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordPlusUNIFORM-
dc.subject.keywordPlusVOLTAGE-
dc.subject.keywordPlusDEVICE-
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