SoC Design Environment with Automated Bus Architecture Generation for Rapid Prototyping with ISS

Abstract

It is important in SoC design that the design and verification can be done easily and quickly. And RTlevel simulation in verification methods is still necessary. But the usage is limited by its low performance. Therefore we propose a SoC verification environment in which hardware parts are accelerated in FPGA and cores are modeled with ISS. To connect ISS in high abstraction level with emulator in pin-level accuracy, bus functional model(BFM) is used. For hardware debugging, bus monitor is designed. By post-processing data from bus monitoring, debugging and performance estimation are possible. To design and verify a design easily and quickly in the proposed environment, we develop a tool which creates bus architectures automatically. With this tool, the design time from specification to FPGA based prototyping can be reduced remarkably. Thus fast verification and design space exploration are possible. AMBA is chosen as the SoC bus protocol.