Comparison of On-chip De-embedding Methods with 28-nm FDSOI MOSFETs up to 110-GHz

Abstract

In this paper, on-chip de-embedding methods are compared by applying to transistor characterization for up to 110-GHz. 2-step and 3-step methods, based on lumped circuit models, and hybrid methods, which are a combination of a cascade model and the lumped circuit model, are studied. For cascade models of the hybrid methods, two sets of de-embedding structures are adopted - (LINE, PAD-LINE) and (THRU LR, THRU LLR) are used for the hybrid-1 method and hybrid-2 method, respectively. A single transistor is used as a device under test (DUT) and all de-embedding patterns for the four methods are implemented with 28-nm fully depleted silicon on insulator (FDSOI) process. Transistor characteristics including gate resistance and parasitic capacitances of FDSOI MOSFETs are extracted and analyzed. In addition, ft and f max of the device are estimated by using the hybrid-1 method.