DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Kwanho | ko |
dc.contributor.author | Lee, Seungjin | ko |
dc.contributor.author | Kim, Joo-Young | ko |
dc.contributor.author | Kim, Minsu | ko |
dc.contributor.author | Kim, Donghyun | ko |
dc.contributor.author | Woo, Jeong-Ho | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2020-10-26T00:56:14Z | - |
dc.date.available | 2020-10-26T00:56:14Z | - |
dc.date.created | 2020-10-12 | - |
dc.date.created | 2020-10-12 | - |
dc.date.issued | 2008-02-03 | - |
dc.identifier.citation | 2008 IEEE International Solid State Circuits Conference, ISSCC, pp.308 - 310 | - |
dc.identifier.issn | 0193-6530 | - |
dc.identifier.uri | http://hdl.handle.net/10203/276963 | - |
dc.description.abstract | A network-on-chip (NoC) is applied to achieve extensive communication bandwidth required for parallel computing. A 125 GOPS NoC-based parallel processor with a bio-inspired visual attention engine (VAE) exploits both data and object-level parallelism while dissipating 583 mW by packet-based power management. The use of more PEs, VAE, and low latency NoC enables higher performance and power efficiency over the previous design. NoC-based parallel processor consisting of 12 IPs: a main processor, 8 PE clusters (PECs), VAE, a matching accelerator (MA), and an external interface. The ARMlO-compatible 32b main processor controls the overall system operations. The VAE detects the feature points on the entire image by neural network algorithms like contour extraction. The 8 PECs perform data-intensive image processing applications such as filtering and histogram calculations. The MA accelerates nearest neighbor search to obtain a final recognition result in real-time. The DMA-like external interface distributes automatically the corresponding image data to each PEC to reduce system overhead. Each core is connected to the NoC via a network interface. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine | - |
dc.type | Conference | - |
dc.identifier.scopusid | 2-s2.0-49549105341 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 308 | - |
dc.citation.endingpage | 310 | - |
dc.citation.publicationname | 2008 IEEE International Solid State Circuits Conference, ISSCC | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Francisco, CA | - |
dc.identifier.doi | 10.1109/ISSCC.2008.4523180 | - |
dc.contributor.localauthor | Kim, Joo-Young | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Kim, Kwanho | - |
dc.contributor.nonIdAuthor | Lee, Seungjin | - |
dc.contributor.nonIdAuthor | Kim, Minsu | - |
dc.contributor.nonIdAuthor | Kim, Donghyun | - |
dc.contributor.nonIdAuthor | Woo, Jeong-Ho | - |
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