DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Yongsun | ko |
dc.contributor.author | Seong, Taeho | ko |
dc.contributor.author | Lee, Jeonghyun | ko |
dc.contributor.author | Hwanq, Chanwoong | ko |
dc.contributor.author | Park, Hangi | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2020-08-27T06:55:33Z | - |
dc.date.available | 2020-08-27T06:55:33Z | - |
dc.date.created | 2020-08-12 | - |
dc.date.created | 2020-08-12 | - |
dc.date.created | 2020-08-12 | - |
dc.date.issued | 2020-02-19 | - |
dc.identifier.citation | 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.266 - 268 | - |
dc.identifier.issn | 0193-6530 | - |
dc.identifier.uri | http://hdl.handle.net/10203/276001 | - |
dc.description.abstract | Methods to detect and correct timing errors of oscillators are very important to achieve the low-jitter performance of a ring-DCO (RDCO) digital PLL (DPLL). A TDC is widely used to quantize these timing errors. The higher the resolution of a TDC, the lower the quantization noise becomes. However, such TDCs require large power to cover a sufficiently wide dynamic range. Instead, [1], [2] presented jitter-minimization techniques that used a bang-bang phase detector (BBPD) and the background optimization of the proportional gain of the loop, KP (top left of Fig. 17.1.1). This approach is effective for low-power designs but is limited in reducing the output jitter, since the information of timing errors by the BBPD is just binary. To overcome this limit, [3] used three parallel BBPDs, each of which had a different time threshold, τ TH . While maintaining the optimal spacing between the τ TH S (instead of decreasing it unconditionally) along with the calibration of K P , the DPLL in [3] succeeded in decreasing the jitter. Despite these efforts, previous DPLLs [1]-[3] had a fundamental limit to minimizing the jitter since they optimized only K Pbased on an incorrect assumption that the RDCO jitter was “white” Gaussian while ignoring flicker noise. However, different from thermal noise, the energy of flicker noise is concentrated at low-frequency offsets near DC, and its effect appears as a random drift of the RDCO frequency over time [4]. Thus, to suppress flicker noise and further reduce the overall jitter, the flicker-induced frequency drifts (f DS ) must be calibrated by adjusting the gain of the integral path, K 1 , as well as K P . | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction | - |
dc.type | Conference | - |
dc.identifier.wosid | 000570129800102 | - |
dc.identifier.scopusid | 2-s2.0-85083826312 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 266 | - |
dc.citation.endingpage | 268 | - |
dc.citation.publicationname | 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Francisco, CA | - |
dc.identifier.doi | 10.1109/ISSCC19947.2020.9062966 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Lee, Yongsun | - |
dc.contributor.nonIdAuthor | Seong, Taeho | - |
dc.contributor.nonIdAuthor | Lee, Jeonghyun | - |
dc.contributor.nonIdAuthor | Hwanq, Chanwoong | - |
dc.contributor.nonIdAuthor | Park, Hangi | - |
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