DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Jong-Hyeok | ko |
dc.contributor.author | Kwon, Kyeongha | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2020-06-26T02:21:38Z | - |
dc.date.available | 2020-06-26T02:21:38Z | - |
dc.date.created | 2020-06-11 | - |
dc.date.created | 2020-06-11 | - |
dc.date.issued | 2018-04 | - |
dc.identifier.citation | IEEE Custom Integrated Circuits Conference (CICC) | - |
dc.identifier.uri | http://hdl.handle.net/10203/274925 | - |
dc.description.abstract | This paper presents a 3.125 Gb/s to 28.125 Gb/s multi-standard channel-independent parallel transceiver. The proposed clock and data recovery (CDR) IC achieves wide tuning range with low clock jitter because a ring oscillator in each channel is injection-locked to an LC VCO in a global clock generator. Each CDR lane generates a channel-independent injection clock signal using a variable clock divider and a highly linear phase rotator. In addition, a frequency tracking loop using a natural frequency detector is proposed to align the frequency of an injection-locked oscillator to the input data rate to suppress a periodic spur under injection. The test chip fabricated in 40nm CMOS achieves a power efficiency of 4.72 mW/Gb/s while generating integrated jitter of 976 ps(rms). | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A 3.125-to-28.125 Gb/s Multi-Standard Transceiver with a Fully Channel-independent Operation in 40nm CMOS | - |
dc.type | Conference | - |
dc.identifier.wosid | 000434207400068 | - |
dc.identifier.scopusid | 2-s2.0-85048128465 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | IEEE Custom Integrated Circuits Conference (CICC) | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Diego, CA | - |
dc.identifier.doi | 10.1109/CICC.2018.8357073 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.contributor.nonIdAuthor | Yoon, Jong-Hyeok | - |
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