A 3 mm x 3 mm Fully Integrated Wireless Power Receiver and Neural Interface System-on-Chip

Abstract

A miniaturized, fully integrated wireless power receiver system-on-chip with embedded 16-channel electrode array and data transceiver for electrocortical neural recording and stimulation is presented. An H-tree power and signal distribution network throughout the SoC maintains high quality factor up to 11 in the on-chip receiver coil at 144 MHz resonant frequency while rejecting RF interference in sensitive neural interface circuits owing to its perpendicular and equidistant geometry. A multi-mode buck-boost resonant regulating rectifier (<formula><tex>$\text{B}^2 \text{R}^3$</tex></formula>) offers greater than 11-dB input dynamic range in RF reception and less than 1 mV overshoot in transient load regulation. At 10 mm link distance, the 9 <formula><tex>$\text{mm}^2$</tex></formula> neural interface SoC fabricated in a 180 nm silicon-on-insulator (SOI) process attains an overall wireless power transmission system efficiency (WSE) of 3.4% in driving a 160 μW load yielding a WSE figure-of-merit of 131, while maintaining signal integrity in analog recording and wireless data transmission that comprise the on-chip load.