DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Chang-Kyo | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2019-12-31T02:20:12Z | - |
dc.date.available | 2019-12-31T02:20:12Z | - |
dc.date.created | 2019-12-30 | - |
dc.date.created | 2019-12-30 | - |
dc.date.created | 2019-12-30 | - |
dc.date.issued | 2019-11 | - |
dc.identifier.citation | IET CIRCUITS DEVICES & SYSTEMS, v.13, no.8, pp.1277 - 1283 | - |
dc.identifier.issn | 1751-858X | - |
dc.identifier.uri | http://hdl.handle.net/10203/270826 | - |
dc.description.abstract | This study demonstrates the noise analysis of a replica driving MDAC architecture, which is verified by implementing a 12-bit 200 MS/s replica driving pipelined analogue-to-digital converter (ADC). Based on the noise design strategy with the target effective number of bits = 10.5-bit, the overall dynamic performance degradation by KT/C noise and thermal noise by an amplifier is alleviated by removing the front-end sample-and-hold (S/H) circuit, and the transconductance (g(m)) of the inner source follower is maximised by increasing the current and threshold voltage (V-T) reduction. Replica input sampling networks are designed for the first-stage sub-ADC and the first-stage MDAC with different aspect ratios to minimise the sampling skew for the S/H-less architecture. A prototype 12-bit 200 MS/s ADC is fabricated in a 65 nm complementary metal oxide semiconductor. The measured spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) at a 1.0 MHz input signal is 82.6 and 65.6 dB, respectively, and SFDR and SNDR at the Nyquist (=99.0 MHz) input are 77.3 and 58.6 dB, respectively. The ADC core and the reference driver consume 53.9 and 13.2 mW, respectively, at a 1.2 V supply voltage. | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC | - |
dc.type | Article | - |
dc.identifier.wosid | 000501602000021 | - |
dc.identifier.scopusid | 2-s2.0-85075892283 | - |
dc.type.rims | ART | - |
dc.citation.volume | 13 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 1277 | - |
dc.citation.endingpage | 1283 | - |
dc.citation.publicationname | IET CIRCUITS DEVICES & SYSTEMS | - |
dc.identifier.doi | 10.1049/iet-cds.2018.5308 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Lee, Chang-Kyo | - |
dc.description.isOpenAccess | Y | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | analogue-digital conversion | - |
dc.subject.keywordAuthor | CMOS integrated circuits | - |
dc.subject.keywordAuthor | thermal noise | - |
dc.subject.keywordAuthor | sample and hold circuits | - |
dc.subject.keywordAuthor | digital-analogue conversion | - |
dc.subject.keywordAuthor | integrated circuit noise | - |
dc.subject.keywordAuthor | driver circuits | - |
dc.subject.keywordAuthor | noise analysis | - |
dc.subject.keywordAuthor | MDAC architecture | - |
dc.subject.keywordAuthor | analogue-to-digital converter | - |
dc.subject.keywordAuthor | dynamic performance degradation | - |
dc.subject.keywordAuthor | thermal noise | - |
dc.subject.keywordAuthor | replica input sampling networks | - |
dc.subject.keywordAuthor | first-stage sub-ADC | - |
dc.subject.keywordAuthor | first-stage MDAC | - |
dc.subject.keywordAuthor | signal-to-noise distortion ratio | - |
dc.subject.keywordAuthor | ADC core | - |
dc.subject.keywordAuthor | pipelined ADC | - |
dc.subject.keywordAuthor | KT-C noise | - |
dc.subject.keywordAuthor | front-end sample-and-hold circuit | - |
dc.subject.keywordAuthor | source follower | - |
dc.subject.keywordAuthor | complementary metal oxide semiconductor | - |
dc.subject.keywordAuthor | spurious-free dynamic range | - |
dc.subject.keywordAuthor | voltage 1 | - |
dc.subject.keywordAuthor | 2 V | - |
dc.subject.keywordAuthor | size 65 | - |
dc.subject.keywordAuthor | 0 nm | - |
dc.subject.keywordAuthor | frequency 1 | - |
dc.subject.keywordAuthor | 0 MHz | - |
dc.subject.keywordAuthor | power 53 | - |
dc.subject.keywordAuthor | 9 mW | - |
dc.subject.keywordAuthor | power 13 | - |
dc.subject.keywordAuthor | 2 mW | - |
dc.subject.keywordAuthor | frequency 99 | - |
dc.subject.keywordAuthor | 0 MHz | - |
dc.subject.keywordAuthor | word length 12 bit | - |
dc.subject.keywordAuthor | word length 10 | - |
dc.subject.keywordAuthor | 5 bit | - |
dc.subject.keywordPlus | SWITCHED-CAPACITOR CIRCUITS | - |
dc.subject.keywordPlus | DB SFDR | - |
dc.subject.keywordPlus | OPAMP | - |
dc.subject.keywordPlus | 10-BIT | - |
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