DC Field | Value | Language |
---|---|---|
dc.contributor.author | Zhang, Jie | ko |
dc.contributor.author | Donofrio, David | ko |
dc.contributor.author | Shalf, John | ko |
dc.contributor.author | Jung, Myoungsoo | ko |
dc.date.accessioned | 2019-12-13T13:26:57Z | - |
dc.date.available | 2019-12-13T13:26:57Z | - |
dc.date.created | 2019-11-28 | - |
dc.date.created | 2019-11-28 | - |
dc.date.created | 2019-11-28 | - |
dc.date.issued | 2015-10-18 | - |
dc.identifier.citation | 24th International Conference on Parallel Architecture and Compilation, PACT 2015, pp.496 - 497 | - |
dc.identifier.uri | http://hdl.handle.net/10203/269653 | - |
dc.description.abstract | General purpose graphics processing units (GPUs) have become a promising solution to process massive data by taking advantages of multithreading. Thanks to thread-level parallelism, GPU-accelerated applications improve the overall system performance by up to 40 times [1], [2], compared to CPU-only architecture. However, data-intensive GPU applications often generate large amount of irregular data accesses, which results in cache thrashing and contention problems [11], [12]. The cache thrashing in turn can introduce a large number of off-chip memory accesses, which not only wastes tremendous energy to move data around on-chip cache and off-chip global memory, but also significantly limits system performance due to many stalled load/store instructions [18], [21].In this work, we redesign the shared last-level cache (LLC) of GPU devices by introducing non-volatile memory (NVM), which can address the cache thrashing issues with low energy consumption. Specifically, we investigate two architectural approaches, one of each employs a 2D planar resistive random-access memory (RRAM) as our baseline NVM-cache and a 3D-stacked RRAM technology [14], [15]. Our baseline NVM-cache replaces the SRAM-based L2 cache with RRAM of similar area size; a memory die consists of eight subarrays, one of which a small fraction of memristor island by constructing 512x512 matrix [13]. Since the feature size of SRAM is around 125 F2 [19] (while that of RRAM around 4 F2 [20]), it can offer around 30x bigger storage capacity than the SRAM-based cache. To make our baseline NVM-cache denser, we proposed 3D-stacked NVM-cache, which piles up four memory layers, and each of them has a single pre-decode logic [16], [17]. | - |
dc.language | English | - |
dc.publisher | ACM and IEEE Computer Society | - |
dc.title | Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing | - |
dc.type | Conference | - |
dc.identifier.wosid | 000378942700049 | - |
dc.identifier.scopusid | 2-s2.0-84975453886 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 496 | - |
dc.citation.endingpage | 497 | - |
dc.citation.publicationname | 24th International Conference on Parallel Architecture and Compilation, PACT 2015 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | The Sir Francis Drake Hotel | - |
dc.identifier.doi | 10.1109/PACT.2015.60 | - |
dc.contributor.localauthor | Jung, Myoungsoo | - |
dc.contributor.nonIdAuthor | Zhang, Jie | - |
dc.contributor.nonIdAuthor | Donofrio, David | - |
dc.contributor.nonIdAuthor | Shalf, John | - |
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