Ghost Routers: Energy-Efficient Asymmetric Multicore Processors with Symmetric NoCs

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dc.contributor.authorSon, yojunko
dc.contributor.authorKim, Hanjoonko
dc.contributor.authorWang, Haoko
dc.contributor.authorKim, Sam Sungko
dc.contributor.authorKim, John Dongjunko
dc.date.accessioned2019-12-13T08:36:14Z-
dc.date.available2019-12-13T08:36:14Z-
dc.date.created2019-11-27-
dc.date.created2019-11-27-
dc.date.created2019-11-27-
dc.date.issued2019-10-17-
dc.identifier.citation13th IEEE/ACM International Symposium on Networks-on-Chip, pp.2:1 - 2:7-
dc.identifier.urihttp://hdl.handle.net/10203/269194-
dc.description.abstractAsymmetric multicore architectures have been proposed to exploit the benefits of heterogeneous cores. However, asymmetric cores present challenge to network-on-chip (NoC) designers since the floorplan is not necessarily regular with "nodes" being different size. In contrast, most of the previously proposed NoC topologies commonly assume a regular or symmetric floorplan with equal size nodes. In this work, we first describe how asymmetric floorplan leads to asymmetric topology and can limit overall performance. To overcome the asymmetric floorplan, we present Ghost Routers - extra "dummy" routers that are added to the NoC to create a symmetric NoC architecture for asymmetric multicore architectures. Ghost router provides higher network path diversity and provides higher network performance that leads to higher system performance. Ghost routers also enable simpler routing algorithms because of the symmetric NoC architecture. While ghost routers is a simplistic modification to the NoC architecture, it does increase NoC cost. However, ghost routers exploit the observations that in realistic systems, the cost of NoC is not a significant fraction of overall system cost. Our evaluations show that ghost routers can improve performance by up to 21% while improving overall energy-efficiency of the system by up to 26%.-
dc.languageEnglish-
dc.publisherIEEE/ACM-
dc.titleGhost Routers: Energy-Efficient Asymmetric Multicore Processors with Symmetric NoCs-
dc.typeConference-
dc.identifier.wosid000526028700002-
dc.identifier.scopusid2-s2.0-85076596284-
dc.type.rimsCONF-
dc.citation.beginningpage2:1-
dc.citation.endingpage2:7-
dc.citation.publicationname13th IEEE/ACM International Symposium on Networks-on-Chip-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationNew York, USA-
dc.identifier.doi10.1145/3313231.3352360-
dc.contributor.localauthorKim, John Dongjun-
dc.contributor.nonIdAuthorKim, Hanjoon-
dc.contributor.nonIdAuthorWang, Hao-
dc.contributor.nonIdAuthorKim, Sam Sung-
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