Standard cell layout design and placement optimization for TFET-based circuits

Abstract

Tunneling Field-Effect Transistors (TFETs) have a potential to decrease supply voltage of integrated circuits thanks to the superior subthreshold swing. However, the source and drain of TFETs are doped in different types (one in n+ and the other in p+), which raises challenges in fabrication in sub-10nm processes. We propose a method to optimize standard cell layouts for TFETs, in which consistent doping profile is maintained in the vertical direction so that design rule violations due to small spacing between implantation masks are resolved. We also notice that the footprints of some standard cells turn out to be rectilinear. A post-placement optimization method to join the cell layouts is also addressed. We finally propose a TFET fabrication process using self-aligned quadruple patterning (SAQP), which can enable TFET fabrication in sub-10nm processes. Our proposed methods bring about 4.5% area reduction, based on experiments with a set of test circuits.