DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.contributor.author | Chang, Dongjin | ko |
dc.date.accessioned | 2019-11-13T01:20:44Z | - |
dc.date.available | 2019-11-13T01:20:44Z | - |
dc.identifier.uri | http://hdl.handle.net/10203/268351 | - |
dc.description.abstract | An electronic circuit includes a reference ADC, a delay circuit, and a main ADC. The reference ADC converts an input signal to an upper bit string of output data, in response to a reference clock. The delay circuit delays a source clock by a delay time to output a main clock. The main ADC converts the input signal to a lower bit string of the output data, in response to the main clock. When a value of the most significant bit included in the lower bit string is identical to a value of the bit which is adjacent to the most significant bit and lower than the most significant bit, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the most significant bit of the lower bit string. | - |
dc.title | Electronic circuit adjusting timing of clock based on bits of output data from sub-ranging analog-to-digital converter | - |
dc.title.alternative | 하위 범위의 아날로그/디지털 컨버터로부터의 약간의 출력 데이터에 기초가 된 클럭의 타이밍을 조절하는 전자 회로 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Chang, Dongjin | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 16194824 | - |
dc.identifier.patentRegistrationNumber | 10454489 | - |
dc.date.application | 2018-11-19 | - |
dc.date.registration | 2019-10-22 | - |
dc.publisher.country | US | - |
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