A Disaggregated Memory System for Deep Learning
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kwon, Youngeun | ko |
| dc.contributor.author | Rhu, Minsoo | ko |
| dc.date.accessioned | 2019-10-02T10:21:21Z | - |
| dc.date.available | 2019-10-02T10:21:21Z | - |
| dc.date.created | 2019-10-01 | - |
| dc.date.created | 2019-10-01 | - |
| dc.date.issued | 2019-09 | - |
| dc.identifier.citation | IEEE MICRO, v.39, no.5, pp.82 - 90 | - |
| dc.identifier.issn | 0272-1732 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/267747 | - |
| dc.description.abstract | As the complexity of deep learning (DL) models scales up, computer architects are faced with a memory "capacity" wall, where the limited physical memory inside the accelerator device constrains the algorithm that can be trained and deployed. This article summarizes our recent work on designing an accelerator-centric, disaggregated memory system for DL. | - |
| dc.language | English | - |
| dc.publisher | IEEE COMPUTER SOC | - |
| dc.title | A Disaggregated Memory System for Deep Learning | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000485731600011 | - |
| dc.identifier.scopusid | 2-s2.0-85069919501 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 39 | - |
| dc.citation.issue | 5 | - |
| dc.citation.beginningpage | 82 | - |
| dc.citation.endingpage | 90 | - |
| dc.citation.publicationname | IEEE MICRO | - |
| dc.identifier.doi | 10.1109/MM.2019.2929165 | - |
| dc.contributor.localauthor | Rhu, Minsoo | - |
| dc.description.isOpenAccess | N | - |
| dc.type.journalArticle | Article | - |
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