DC Field | Value | Language |
---|---|---|
dc.contributor.author | Moon, Kyoung-Jun | ko |
dc.contributor.author | Jo, Dong-Shin | ko |
dc.contributor.author | Kim, Wan | ko |
dc.contributor.author | Choi, Michael | ko |
dc.contributor.author | Ko, Hyung-Jong | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2019-09-17T07:20:11Z | - |
dc.date.available | 2019-09-17T07:20:11Z | - |
dc.date.created | 2019-09-17 | - |
dc.date.created | 2019-09-17 | - |
dc.date.issued | 2019-09 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2532 - 2542 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/267524 | - |
dc.description.abstract | This paper introduces a current-mode residue processing technique in a pipelined-successive-approximation register (SAR) analog-to-digital converter (ADC), which extends the operation speed of a single-channel ADC utilizing low-impedance-based signaling. A 10-bit pipelined-SAR ADC with featured building blocks such as a degenerated gm-cell as an open-loop residue amplifier, a switched-current mirror for sample-and-hold (S/H) function, and a split current digital-to-analog converter (DAC) for current-domain SAR conversion achieves a 500-MS/s conversion-rate under a 1.0-V supply. With background inter-stage mismatch calibration, a prototype ADC fabricated in a 28-nm CMOS process achieves 56.6-dB signal-to-noise-and-distortion ratio (SNDR) at a Nyquist input, resulting in a Walden figure of merit (FoM) of a 21.7-fJ/conversion-step. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000482625000016 | - |
dc.identifier.scopusid | 2-s2.0-85071606680 | - |
dc.type.rims | ART | - |
dc.citation.volume | 54 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 2532 | - |
dc.citation.endingpage | 2542 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2019.2926648 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Jo, Dong-Shin | - |
dc.contributor.nonIdAuthor | Kim, Wan | - |
dc.contributor.nonIdAuthor | Choi, Michael | - |
dc.contributor.nonIdAuthor | Ko, Hyung-Jong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Analog to digital converter (ADC) | - |
dc.subject.keywordAuthor | current-domain | - |
dc.subject.keywordAuthor | current-mode residue processing | - |
dc.subject.keywordAuthor | gm-cell | - |
dc.subject.keywordAuthor | open-loop amplifier | - |
dc.subject.keywordAuthor | pipelined-successive-approximation register (SAR) | - |
dc.subject.keywordAuthor | split current digital-to-analog converter (DAC) | - |
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